共 50 条
- [2] Logical not polynomial forms to represent multiple-valued functions [J]. 1996 26TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS, 1996, : 302 - 307
- [4] Residue arithmetic circuits based on the signed-digit multiple-valued arithmetic circuits [J]. 1998 28TH IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC - PROCEEDINGS, 1998, : 276 - 281
- [6] AN INTEGER-VALUED ARITHMETIC FUNCTION WITH NO INFINITE LINEAR SUBSET [J]. AMERICAN MATHEMATICAL MONTHLY, 1965, 72 (04): : 427 - &
- [7] Systematic interpretation of redundant arithmetic adders in binary and multiple-valued logic [J]. IEICE TRANSACTIONS ON ELECTRONICS, 2006, E89C (11): : 1645 - 1654
- [8] Reconfigurable current-mode multiple-valued residue arithmetic circuits [J]. 1998 28TH IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC - PROCEEDINGS, 1998, : 282 - 287
- [9] Synthesis of multiple-valued arithmetic circuits using Evolutionary Graph Generation [J]. 31ST INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS, 2001, : 253 - 258