Synthesis of High-Speed Finite State Machines in FPGAs by State Splitting

被引：5

作者：

Salauyou, Valery ^{[1
]}

机构：

[1] Bialystok Tech Univ, Fac Comp Sci, Bialystok, Poland

来源：

COMPUTER INFORMATION SYSTEMS AND INDUSTRIAL MANAGEMENT, CISIM 2016 | 2016年 / 9842卷

关键词：

Synthesis; Finite state machine; High-speed; High performance; State splitting; Field programmable gate array; Look up table;

D O I：

10.1007/978-3-319-45378-1_64

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

A synthesis method of high-speed finite state machines (FSMs) in field programmable gate arrays (FPGAs) based on LUT (Look Up Table) by internal state splitting is offered. The method can be easily included in designing the flow of digital systems in FPGA. Estimations of the number of LUT levels are presented for an implementation of FSM transition functions in the case of sequential and parallel decomposition. Split algorithms of FSM internal states for the synthesis of high-speed FSMs are described. The experimental results showed a high efficiency of the offered method. FSM performance increases by 1.52 times on occasion. In conclusion, the experimental results were considered, and prospective directions for designing high-speed FSMs are specified.

引用

页码：741 / 751

页数：11

共 50 条

[1] High-speed finite-state machines
Hoff, B
[J]. DR DOBBS JOURNAL, 1997, 22 (11): : 54 - +
[2] Synthesis method of high speed finite state machines
Czerwinski, R.
Kania, D.
[J]. BULLETIN OF THE POLISH ACADEMY OF SCIENCES-TECHNICAL SCIENCES, 2010, 58 (04) : 635 - 644
[3] STATE OF THE DEVELOPMENT OF HIGH-SPEED TISSUE MACHINES
FREI, HP
[J]. WOCHENBLATT FUR PAPIERFABRIKATION, 1980, 108 (22): : 917 - 919
[4] Finite state machines for information collection and assessment on high-speed data networks
Hershey, PC
Silio, CB
[J]. PROCEEDINGS OF THE IASTED INTERNATIONAL CONFERENCE ON WIRELESS AND OPTICAL COMMUNICATIONS, 2002, : 499 - 506
[5] Reconfigurable models of finite state machines and their implementation in FPGAs
Sklyarov, V
[J]. JOURNAL OF SYSTEMS ARCHITECTURE, 2002, 47 (14-15) : 1043 - 1064
[6] State-of-the-Art High-Speed Switched Reluctance Machines
Fairall, Earl W.
Bilgin, Berker
Emadi, Ali
[J]. 2015 IEEE INTERNATIONAL ELECTRIC MACHINES & DRIVES CONFERENCE (IEMDC), 2015, : 1621 - 1627
[7] State Merging and Splitting Strategies for Finite State Machines Implemented in FPGA
Klimowicz, Adam
Salauyou, Valery
[J]. APPLIED SCIENCES-BASEL, 2022, 12 (16):
[8] Synthesis of finite state machines for improved state verification
Ahmad, InItiaz
Ali, Faridah M.
Das, A. Shoba
[J]. COMPUTERS & ELECTRICAL ENGINEERING, 2006, 32 (05) : 349 - 363
[9] SYNTHESIS OF FINITE STATE MACHINES FOR CPLDs
Czerwinski, Robert
Kania, Dariusz
[J]. INTERNATIONAL JOURNAL OF APPLIED MATHEMATICS AND COMPUTER SCIENCE, 2009, 19 (04) : 647 - 659
[10] On Using Speed as the Criteria of State Selection for Minimization of Finite State Machines
Klimowicz, Adam
[J]. COMPUTER INFORMATION SYSTEMS AND INDUSTRIAL MANAGEMENT, CISIM 2016, 2016, 9842 : 493 - 503

← 1 2 3 4 5 →