An improved digital timing recovery circuit for burst-mode communications

被引：0

作者：

Liu, Changqing ^{[1
]}

Guo, Xingbo ^{[1
]}

Song, Jian ^{[1
]}

Pan, Changyong ^{[1
]}

Yang, Zhixing ^{[1
]}

机构：

[1] Tsinghua Univ, Dept Elect Engn, Beijing 100084, Peoples R China

来源：

2006 IEEE INTERNATIONAL CONFERENCE ON WIRELESS COMMUNICATIONS, NETWORKING AND MOBILE COMPUTING, VOLS 1-4 | 2006年

关键词：

burst-mode communication; bang-bang phase detector; phase lock loop (PLL); acquisition time;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Burst-mode communication (or burst-mode transmission) has been increasingly adopted in modern wireless communication systems. It requires a digital timing recovery circuit with short acquisition time. The bang-bang phase detector is widely used in digital timing recovery circuits owing to its simple structure. However these timing recovery circuits do not provide a quick acquisition. In this paper an enhanced bang-bang phase detector is proposed increasing the resolution of the timing error by over-sampling the data L times and therefore reducing the phase error variance by 1/L(2) times. This timing recovery scheme can be implemented using a Direct Digital Synchronizer (DDS). Both simulation and experimental results illustrate that the new scheme has a shorter acquisition time and a longer holding time, satisfying the need of burst-mode communications.

引用

页码：666 / 670

页数：5

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