One mask architecture for 3D front-end integration

被引：0

作者：

Coronel, P. ^{[1
]}

Arnaud, F. ^{[1
]}

Harrison, S. ^{[2
]}

Wacquez, R. ^{[1
]}

Bustos, J. ^{[1
]}

Pouydebasque, A. ^{[2
]}

Borot, B. ^{[1
]}

Gallon, C. ^{[1
]}

Fenouillet-Beranger, C. ^{[3
]}

Pain, L. ^{[3
]}

Delille, D. ^{[2
]}

Bourdon, H. ^{[1
]}

Borel, S. ^{[3
]}

Arnal, V. ^{[1
]}

Ferreira, P. ^{[1
]}

Lenoble, D. ^{[1
]}

Skotnicki, T. ^{[1
]}

机构：

[1] STMicroelect, F-38926 Crolles, France

[2] NXP Semiconduct, F-38926 Crolles, France

[3] CEA Grenoble, LETI Minatec, F-38054 Grenoble, France

来源：

ULIS 2008: PROCEEDINGS OF THE 9TH INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON | 2008年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper demonstrates the possibility to use a Bottom-Up front-end (FE) architecture for sub-32nm CMOS nodes with a new 3D approach in front-end flow. This architecture based on the so called FRETCH (Film Replacement Etching Through Contact Hole) solution [1] is compatible to adapt a specific device before or after electrical test. To address the full 3D in FE concept of buried integration will be proposed by using e-beam and HSQ material. Finally a novel integration scheme fully compatible with conventional bulk flow with one mask will be depicted allowing a self assembly structure and reducing significantly the process variability.

引用

页码：35 / +

页数：3

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