Universal Chiplet Interconnect Express (UCIe): An Open Industry Standard for Innovations With Chiplets at Package Level

被引：46

作者：

Das Sharma, Debendra ^{[1
]}

Pasdast, Gerald ^{[1
]}

Qian, Zhiguo ^{[2
]}

Aygun, Kemal ^{[1
]}

机构：

[1] Intel Corp, Santa Clara, CA 95052 USA

[2] Intel Corp, Chandler, AZ 85226 USA

来源：

IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY | 2022年 / 12卷 / 09期

关键词：

Clocks; Packaging; Standards; Protocols; Integrated circuit interconnections; Delays; Training; Accelerator; availability; chiplet; compute express link; co-packaged optics; memory expansion; packaging; Peripheral Component Interconnect (PCI) Express; pooling; power-efficiency; rack scale architecture; reliability;

D O I：

10.1109/TCPMT.2022.3207195

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

Universal Chiplet Interconnect Express (UCIe) is an open industry standard interconnect for developing an open chiplet ecosystem, where chiplets from any supplier can be packaged anywhere in an interoperable manner. This article delves into the architectural, circuit, channel, and packaging aspects that we developed that has been adopted in the UCIe 1.0 Specification. We present our results based on our channel and circuit implementation studies.

引用

页码：1423 / 1431

页数：9

共 9 条

[1] System on a Package Innovations With Universal Chiplet Interconnect Express (UCIe) Interconnect
Das Sharma, Debendra
IEEE MICRO, 2023, 43 (02) : 76 - 85
[2] Universal Chiplet Interconnect Express Γ (UCIeΓ)
Moore G.E.
Advancing Microelectronics, 2023, 2023 (DPC): : 49 - 60
[3] Universal Chiplet Interconnect Express: An Open Industry Standard for Memory and Storage Applications
Das Sharma, Debendra
Coughlin, Thomas
COMPUTER, 2024, 57 (01) : 75 - 81
[4] Signal Integrity Design and Analysis of Universal Chiplet Interconnect Express (UCIe) Channel in Silicon Interposer for Advanced Package
Shin, Taein
Kim, Keunwoo
Park, Hyunwook
Sim, Boogyo
Kim, Seongguk
Kim, Jihun
Choi, Seonguk
Park, Joonsang
Song, Jinwook
Kim, Jaehyup
Park, Joung Won
Kang, Daehyun
Kim, Joungho
IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS, EDAPS 2023, 2023,
[5] Level 4 Autonomous Driving SoC, leveraging chiplet, advanced package and UCIe
Agrawal, Vinayak
Piednoel, Francois
Elkanovich, Igor
Sil, Dwaipayan
Jahan, Mirza
2023 IEEE SYMPOSIUM ON HIGH-PERFORMANCE INTERCONNECTS, HOTI, 2023, : 9 - 14
[6] The Significance of Thermal-Aware Universal Chiplet Interconnect Express (UCIe) Interface Design in 2.5D/3D ICs
Son, Keeyoung
Kim, Keunwoo
Choi, Seonguk
Yoon, Jiwon
Kim, Jihun
Hong, Jonghyun
Kim, Hyunwoo
Lee, Junghyun
Kim, Joungho
IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS, EDAPS 2023, 2023,
[7] High-performance, power-efficient three-dimensional system-in-package designs with universal chiplet interconnect express
Debendra Das Sharma
Gerald Pasdast
Sathya Tiagaraj
Kemal Aygün
Nature Electronics, 2024, 7 : 244 - 254
[8] High-performance, power-efficient three-dimensional system-in-package designs with universal chiplet interconnect express
Das Sharma, Debendra
Pasdast, Gerald
Tiagaraj, Sathya
Aygun, Kemal
NATURE ELECTRONICS, 2024, 7 (03) : 244 - 254
[9] Compute Express Link®: An open industry-standard interconnect enabling heterogeneous data-centric computing
Das Sharma, Debendra
2022 IEEE SYMPOSIUM ON HIGH-PERFORMANCE INTERCONNECTS (HOTI), 2022, : 5 - 12

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