Design verification of Web Applications using symbolic model checking

被引:0
|
作者
Di Sciascio, E [1 ]
Donini, FM
Mongiello, M
Totaro, R
Castelluccia, D
机构
[1] Politecn Bari, Dipartimento Elettrotech & Elettron, Bari, Italy
[2] Univ Tuscia, Viterbo, Italy
来源
WEB ENGINEERING, PROCEEDINGS | 2005年 / 3579卷
关键词
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Fast and reliable development of Web Applications (WA) calls for methods that address systematic design, and tools that cover all the aspects of the design process and complement the current implementation technologies. To ensure the reliability of WA it is important that they be validated and verified at early design phase. We focus on black-box, automated verification of the UML design of a WA using Model Checking techniques.
引用
收藏
页码:69 / 74
页数:6
相关论文
共 50 条
  • [1] Web applications design and maintenance using symbolic model checking
    Di Sciascio, E
    Donini, FM
    Mongiello, M
    Piscitelli, G
    [J]. SEVENTH EUROPEAN CONFERENCE ON SOFTWARE MAINTENANCE AND REENGINEERING, PROCEEDINGS, 2003, : 63 - 72
  • [2] Formal verification of digital circuits using symbolic model checking
    Casar, A
    Brezocnik, Z
    Kapus, T
    [J]. INFORMACIJE MIDEM-JOURNAL OF MICROELECTRONICS ELECTRONIC COMPONENTS AND MATERIALS, 2000, 30 (03): : 153 - 160
  • [3] Verification of CTLBDI Properties by Symbolic Model Checking
    Chen, Ran
    Zhang, Wenhui
    [J]. 2019 26TH ASIA-PACIFIC SOFTWARE ENGINEERING CONFERENCE (APSEC), 2019, : 102 - 109
  • [4] Symbolic simulation as a simplifying strategy for SoC verification with symbolic model checking
    Dumitrescu, E
    Borrione, D
    [J]. 3RD IEEE INTERNATIONAL WORKSHOP ON SYSTEM-ON-CHIP FOR REAL-TIME APPLICATIONS, PROCEEDINGS, 2003, : 378 - 383
  • [5] Design verification by model checking
    [J]. 1600, Japan Society for Software Science and Technology (31):
  • [6] Scalable software model checking using design for verification
    Bultan, Tevfik
    Betin-Can, Aysu
    [J]. VERIFIED SOFTWARE: THEORIES, TOOLS, EXPERIMENTS, 2008, 4171 : 337 - 346
  • [7] Formal Verification of SDG via Symbolic Model Checking
    Ning, Ning
    Zhang, Jun
    Gao, Xiang-Yang
    Xue, Jing
    [J]. ICICTA: 2009 SECOND INTERNATIONAL CONFERENCE ON INTELLIGENT COMPUTATION TECHNOLOGY AND AUTOMATION, VOL IV, PROCEEDINGS, 2009, : 521 - 524
  • [8] Design constraints in symbolic model checking
    Kaufmann, M
    Martin, A
    Pixley, C
    [J]. COMPUTER AIDED VERIFICATION, 1998, 1427 : 477 - 487
  • [9] SYMBOLIC MODEL CHECKING FOR SEQUENTIAL-CIRCUIT VERIFICATION
    BURCH, JR
    CLARKE, EM
    LONG, DE
    MCMILLAN, KL
    DILL, DL
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1994, 13 (04) : 401 - 424
  • [10] Verification of a logically controlled, solids transport system using symbolic model checking
    Probst, ST
    Powers, GJ
    Long, DE
    Moon, I
    [J]. COMPUTERS & CHEMICAL ENGINEERING, 1997, 21 (04) : 417 - 429