A parallel algorithm for minimum cost path computation on polymorphic processor array

被引:0
|
作者
Baglietto, P
Maresca, M
Migliardi, M
机构
[1] Univ Genoa, DIST, I-16145 Genoa, Italy
[2] Univ Padua, Dept Elect & Informat, Padua, Italy
来源
关键词
D O I
暂无
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
This paper describes a new parallel algorithm for Minimum Cost Path computation on the Polymorphic Processor Array, a massively parallel architecture based on a reconfigurable mesh interconnection network. The proposed algorithm has been implemented using the Polymorphic Parallel C language and has been validated through simulation. The proposed algorithm for the Polymorphic Processor Array, delivers the same performance, in terms of computational complexity, as the hypercube interconnection network of the connection Machine, and as the Gated Connection Network.
引用
收藏
页码:13 / 18
页数:6
相关论文
共 50 条
  • [1] PARALLEL PATH PLANNING ON THE DISTRIBUTED ARRAY PROCESSOR
    SHU, C
    BUXTON, H
    PARALLEL COMPUTING, 1995, 21 (11) : 1749 - 1767
  • [2] Design and Development of Low Cost Multicore Processor for Parallel Computation
    Bansal, Ankit
    Saini, Prerna
    2016 2ND INTERNATIONAL CONFERENCE ON COMMUNICATION CONTROL AND INTELLIGENT SYSTEMS (CCIS), 2016, : 217 - 222
  • [3] A Systolic Array Based GTD Processor With a Parallel Algorithm
    Yang, Chia-Hsiang
    Chou, Chun-Wei
    Hsu, Chia-Shen
    Chen, Chiao-En
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2015, 62 (04) : 1099 - 1108
  • [4] COMPUTATIONAL COST OF IMAGE REGISTRATION WITH A PARALLEL BINARY ARRAY PROCESSOR
    REEVES, AP
    ROSTAMPOUR, A
    IEEE TRANSACTIONS ON PATTERN ANALYSIS AND MACHINE INTELLIGENCE, 1982, 4 (04) : 449 - 455
  • [5] THE PARALLEL COMPUTATION OF MINIMUM COST PATHS IN GRAPHS BY STREAM CONTRACTION
    PAN, V
    REIF, J
    INFORMATION PROCESSING LETTERS, 1991, 40 (02) : 79 - 83
  • [6] Shortest partial path first algorithm for reconfigurable processor array with faults
    Wu, Jigang
    Liu, Ningjing
    Lam, Siew-Kei
    Jiang, Guiyuan
    2016 IEEE TRUSTCOM/BIGDATASE/ISPA, 2016, : 1198 - 1203
  • [7] Parallel blocked algorithm for solving the algebraic path problem on a matrix processor
    Takahashi, A
    Sedukhin, S
    HIGH PERFORMANCE COMPUTING AND COMMUNICATIONS, PROCEEDINGS, 2005, 3726 : 786 - 795
  • [8] Parallel processor algorithm for variable block-size computation at low bitrates
    Koskinen, L
    Halonen, K
    Paasio, A
    2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 4122 - 4125
  • [9] A Minimum Cost Active and Backup Path Algorithm with SRLG Constraints
    Zhang, Jianhui
    Wang, Bin
    Wang, Binqiang
    Ren, Jinqiu
    PROCEEDINGS OF THE 2009 PACIFIC-ASIA CONFERENCE ON CIRCUITS, COMMUNICATIONS AND SYSTEM, 2009, : 396 - 400
  • [10] A dedicated parallel processor for fuzzy computation
    Ascia, G
    Catania, V
    PROCEEDINGS OF THE SIXTH IEEE INTERNATIONAL CONFERENCE ON FUZZY SYSTEMS, VOLS I - III, 1997, : 787 - 792