Modeling litho-constrained design layout

This paper derived a method of modeling litho-constrained layout in design stage. The model applies directly on design layout and does not require mask-synthesis steps. Results show we can capture design-relevant litho "hot-spots" within a matter of an hour on a large full-chip data. This method proves that the hot-spot information is embedded in original design layout and can be extracted with strong signal. This method enables a designer to correct real hot-spots before tape-out. It provides a mechanism to quantify the sensitivity of layout configuration to lithography printability and to guide OPC to focus on litho-sensitive regions.