CMOS LNA design for LEO space S-Band applications

In this study, LNAs for low earth orbit (LEO) S-Band uplink/downlink "System-on-Chip" receiver stages with different topologies are designed and simulated using the Mietec CMOS 0.7mum process and the Cadence/BSIM3v3 tool. Some of these topologies have been studied over CMOS process for the first time in literature. The simulation results of one of the LNA designs, with no parasitic effects, provides a forward gain of 18.5 dB with noise figure of 2 dB while drawing 18mW from +3 V supply at 2210 MHz. When layout parasitic effects are included the forward gain decreases to 9 dB while noise figure increases to 4.5 dB. The area occupied is 1.8mm*1.6mm with pads, 1.3mm*1.2mm without pads. It is dominated by three inductors that are surrounded by grounded guard rings and have patterned ground shield (PGS) under them, while the active devices and resistors occupy only a small section.