Applying march tests to k-way set-associative cache memories

被引：6

作者：

Alpe, Simone ^{[1
]}

Di Carlo, Stefano ^{[1
]}

Prinetto, Paolo ^{[1
]}

Savino, Alessandro ^{[1
]}

机构：

[1] Politecn Torino, Dep Control & Comp Engn, Turin, Italy

来源：

PROCEEDINGS OF THE 13TH IEEE EUROPEAN TEST SYMPOSIUM: ETS 2008 | 2008年

关键词：

D O I：

10.1109/ETS.2008.25

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Embedded microprocessor cache memories stiffer front limited observability and controllability, creating problems during in-system test. The application of test algorithms for SRAM memories to cache memories thus requires opportune transformations. In this paper we present a procedure to adapt traditional march tests to testing the data and the directory array of k-way set-associative cache memories with LRU replacement. The basic idea is to translate each march test operation into an equivalent sequence of cache operations able to reproduce the desired marching sequence into the data and the directory, array of the cache.

引用

页码：77 / 83

页数：7

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