The Fully-Serial Pipelined Multiplier

被引：0
|
作者：
Shafer, Andrew G. [1 ]
Parker, Lyndsi R. [2 ]
Swartzlander, Earl E., Jr. [3 ]
机构：
[1] Adv Micro Devices Inc, 7171 Southwest Pkwy, Austin, TX 78735 USA
[2] IBM Corp, Austin, TX 78753 USA
[3] Univ Texas Austin, Austin, TX 78712 USA
来源：
2011 CONFERENCE RECORD OF THE FORTY-FIFTH ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS & COMPUTERS (ASILOMAR) | 2011年
关键词：
Parallel Counter; fully-serial multiplication; sign-magnitude multiplication; two's complement multiplication; OUTPUT; INPUT;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents a new multiplier design which is fully-serial and requires only 1.5N cycles to return a product. This design has been implemented for both unsigned and two's complement number systems. This design can be pipelined so that each additional multiplication only requires N cycles.
引用
收藏
页码：1817 / 1822
页数：6
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