High-bandwidth address translation for multiple-issue processors

被引：0
|
作者：
Austin, TM [1 ]
Sohi, GS [1 ]
机构：
[1] UNIV WISCONSIN,DEPT COMP SCI,MADISON,WI 53706
来源：
23RD ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, PROCEEDINGS | 1996年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
引用
收藏
页码：158 / 167
页数：10
相关论文
共 50 条
  • [1] A high-bandwidth memory pipeline for wide issue processors
    Cho, S
    Yew, PC
    Lee, G
    IEEE TRANSACTIONS ON COMPUTERS, 2001, 50 (07) : 709 - 723
  • [2] On high-bandwidth data cache design for multi-issue processors
    Rivers, JA
    Tyson, GS
    Davidson, ES
    Austin, TM
    THIRTIETH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, PROCEEDINGS, 1997, : 46 - 56
  • [3] High-bandwidth Address Generation Unit
    Galuzzi, Carlo
    Gou, Chunyang
    Calderon, Humberto
    Gaydadjiev, Georgi N.
    Vassiliadis, Stamatis
    JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2009, 57 (01): : 33 - 44
  • [4] High-bandwidth address generation unit
    Calderon, Humberto
    Galuzzi, Carlo
    Gaydadjiev, Georgi
    Vassiliadis, Stamatis
    EMBEDDED COMPUTER SYSTEMS: ARCHITECTURES, MODELING, AND SIMULATION - PROCEEDINGS, 2007, 4599 : 251 - +
  • [5] High-bandwidth Address Generation Unit
    Carlo Galuzzi
    Chunyang Gou
    Humberto Calderón
    Georgi N. Gaydadjiev
    Stamatis Vassiliadis
    Journal of Signal Processing Systems, 2009, 57 : 33 - 44
  • [6] MPS: Miss-path scheduling for multiple-issue processors
    Banerjia, S
    Sathaye, SW
    Menezes, KN
    Conte, TM
    IEEE TRANSACTIONS ON COMPUTERS, 1998, 47 (12) : 1382 - 1397
  • [7] Non-sequential instruction cache prefetching for multiple-issue processors
    Veidenbaum, AV
    Zhao, QB
    Shameer, A
    INTERNATIONAL JOURNAL OF HIGH SPEED COMPUTING, 1999, 10 (01): : 115 - 140
  • [8] Reconfigurable Custom Functional Unit Generation and Exploitation for Multiple-Issue Processors
    Wu, I-Wei
    Shann, Jean Jyh-Jiun
    Chung, Chung-Ping
    JOURNAL OF INFORMATION SCIENCE AND ENGINEERING, 2015, 31 (04) : 1431 - 1453
  • [9] HIGH-BANDWIDTH INTERLEAVED MEMORIES FOR VECTOR PROCESSORS - A SIMULATION STUDY
    SOHI, GS
    IEEE TRANSACTIONS ON COMPUTERS, 1993, 42 (01) : 34 - 44
  • [10] HIGH-BANDWIDTH DATA MEMORY-SYSTEMS FOR SUPERSCALAR PROCESSORS
    SOHI, GS
    FRANKLIN, M
    SIGPLAN NOTICES, 1991, 26 (04): : 53 - 62
12345