Hardware Trojan Detection by Delay and Electromagnetic Measurements

被引：0

作者：

Ngo, X-T. ^{[2
]}

Exurville, I. ^{[1
,5
]}

Bhasin, S. ^{[2
]}

Danger, J-L. ^{[2
,3
,4
]}

Guilley, S. ^{[2
,3
,4
]}

Najm, Z. ^{[2
]}

Rigaud, J-B. ^{[5
]}

Robisson, B. ^{[1
]}

机构：

[1] CEA Tech PACA, LSAS, Gardanne, France

[2] TELECOM ParisTech, Paris, France

[3] Secure IC SAS, Paris, France

[4] Secure IC SAS, Rennes, France

[5] EMSE, LSAS, Gardanne, France

来源：

2015 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE) | 2015年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Hardware Trojans (HT) inserted in integrated circuits have received special attention of researchers. In this paper, we present firstly a novel HT detection technique based on path delays measurements. A delay model, which considers intra-die process variations, is established for a net. Secondly, we show how to detect HT using ElectroMagnetic (EM) measurements. We study the HT detection probability according to its size taking into account the inter-die process variations with a set of FPGA. The results show, for instance, that there is a probability greater than 95% with a false negative rate of 5% to detect a HT larger than 1.7% of the original circuit.

引用

页码：782 / 787

页数：6

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