Suppression of gate depletion in p+-polysilicon-gated sub-40 nm pMOSFETs by laser thermal processing

Laser thermal processing (LTP) was investigated as a gate pre-annealing technique and its advantages over rapid thermal annealing (RTA) with regard to both gate activation and suppression of boron penetration were confirmed by evaluating the electrical characteristics of sub-40nm p-metal oxide semiconductor field effect transistors (pMOSFETs). Laser annealing transformed amorphous Si in which high doses of boron were implanted into poly-Si with highly activated boron profiles down to the gate/gate oxide interface. By suppressing gate depletion with suppressing boron penetration, LTP results in an on-current at I-off = 70 [nA/mu m] that is 4% greater than that in a device fabricated using conventional RTA. The off-state I-g current that flows mainly from the p(+) poly-Si gate to the drain overlap region is smaller in devices fabricated using LTP because the reduced roughness of the poly-Si gate/gate oxide interface in these devices reduces the local electric field enhancement.