Low-Power Design Techniques for Rx RF Front-End

This paper presents the design and implementation of low-power CMOS radio-frequency (RF) receiver (Rx) building blocks that operate at 2.4 GHz. The design approach exploits the biasing of MOS devices in their moderate inversion region to optimize the trade-off between the performance and the power consumption. A cascade of a low-noise amplifier (LNA) and a mixer achieves a voltage gain of 31.4 dB, and a noise figure (NF) of 6.8 dB while consuming 360 mu W. A 101 mu W voltage-controlled oscillator (VCO) is also demonstrated. Several low-power architectures, including a combination of an LNA with a VCO, are also presented. A proof-of-concept prototype for the combined LNA-VCO is implemented in a 0.13-mu m CMOS process. The circuit consumes 240 mu W from a 0.8 V supply, and achieves a gain of 18.3 dB, an NF of 3.2 dB and a phase noise of -115.4 dBc/Hz at 1 MHz offset.