Suppression of Die-to-Die Delay Variability of Silicon on Thin Buried Oxide (SOTB) CMOS Circuits by Balanced P/N Drivability Control with Back-Bias for Ultralow-Voltage (0.4 V) Operation

被引：0

作者：

Makiyama, H. ^{[1
]}

Yamamoto, Y. ^{[1
]}

Shinohara, H. ^{[1
]}

Iwamatsu, T. ^{[1
]}

Oda, H. ^{[1
]}

Sugii, N. ^{[1
]}

Ishibashi, K. ^{[3
]}

Mizutani, T. ^{[2
]}

Hiramoto, T. ^{[2
]}

Yamaguchi, Y. ^{[1
]}

机构：

[1] Low Power Elect Assoc & Project, West 7,16-1 Onogawa, Tsukuba, Ibaraki 3058569, Japan

[2] Univ Tokyo, Tsukuba, Ibaraki 3058569, Japan

[3] Univ Electrocommun, Tsukuba, Ibaraki, Japan

来源：

2013 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2013年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Small-variability transistors such as silicon on thin buried oxide (SOTB) are effective for reducing the operation voltage (V-dd). In the ultralow-V-dd regime, however, the upsurging delay (tau(pd)) variability is the most important challenge. This paper proposes the balanced n/p drivability control method for reducing the die-to-die delay variation by back bias applicable for various circuits. Excellent variability reduction by this balanced control is demonstrated at V-dd = 0.4 V.

引用

页数：4