Word-parallel Associative Memory for k-Nearest-Neighbor with Configurable Storage Space of Reference Vectors

Apart from the speed performance, a common IC-implementation problem for nearest neighbor search, one of the most basic algorithms in pattern recognition, is low flexibility to different task applications. We report a digital word-parallel associative memory architecture with reconfigurable storage-space of reference vectors and clock-counting-based nearest-Euclidean-distance search, enabling single-chip implementation of k-nearest-neighbor (kNN) classification and configuration for many different applications. The main time-consuming part of kNN, the clock-based minimal-distance searching, is carried out by weighted frequency dividers that drastically reduce the in principle exponential increase of the worst-case search-clock number with the bit width of vector components to only a linear increase. This clock-based search concept achieves thus high classification speed, good area-efficiency and low power dissipation. In general, an IC implementation has limited flexibility after manufacturing. The proposed programmable switching circuits, which are located between groups of vector components, enable flexibility of reference feature-vector dimension and number at the same time. After k minimal distance searching, a dedicated circuit for majority vote is used to assign the unknown input to the class with the highest vote value. A test chip in 180 nm CMOS technology, which has 32 rows, 4 elements in each row and 2 8-bit components in each element, achieves low power dissipation of 61.4 mW (at 45.58 MHz and 1.8 V). In particular, the reconfigurable distance search circuit consumes only 11.9 mW.