FPGA Implementation of Efficient AES Encryption

被引：0
|
作者：
Priya, S. Sridevi Sathya [1 ]
Kumar, P. Karthigai [2 ]
SivaMangai, N. M. [1 ]
Rejula, V. [1 ]
机构：
[1] Karunya Univ, Dept Elect & Commun Engn, Coimbatore, Tamil Nadu, India
[2] Karpagam Coll Engn, Dept Elect & Commun Engn, Coimbatore, Tamil Nadu, India
来源：
2015 INTERNATIONAL CONFERENCE ON INNOVATIONS IN INFORMATION, EMBEDDED AND COMMUNICATION SYSTEMS (ICIIECS) | 2015年
关键词：
AES; increased Parallelism; throughput; latency; high throughput; DESIGN;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, a high throughput modified Advanced Encryption Standard (AES)-128 bit algorithm is implemented. A new increased parallelism technique is introduced in modified AES architecture in Mix Column round which increases the overall throughput of AES algorithm. This technique is implemented in XC5VLX50T FPGA device Virtex-5. Using this technique throughput is increased 5 % and area is decreased by 30 % when compared to parallel mixcolumn.
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页数：4
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