An on-pixel FPN reduction method for a high dynamic range CMOS imager

A high dynamic range CMOS image sensor implementing a fixed pattern noise (FPN) reduction method is presented. The high dynamic range is reach through a logarithmic architecture pixel. An on-chip calibration method is implemented to reduce the FPN caused by process variations, weakness of this architecture. The basic principle is the calibration of each pixel against an in-pixel reference current in place of the diode photocurrent. Two pixel levels corresponding to the photocurrent and a known reference current become available for every pixel. Then a double sampling technique allows removing offsets due to threshold voltage variations. An innovation of this work consists in the implementation of the current calibration source totally inside the pixel, allowing a better precision of the FPN compensation and lower power consumption. This FPN reduction method is performed while keeping only four transistors per pixel. A 128x128 pixels test chip has been designed and fabricated in 0.35 mu m, 3.3V CMOS standard technology. Pixel measures 1Ox10.6 mu m(2) with a fill factor of 33%. The dynamic range is up to 100dB with a frame rate up to 30 images per second and a measured FPN of 2.9%rms of the total dynamic range.