An FPGA Implementation of 4x4 Arbiter PUF

被引：1

作者：

Aknesil, Can ^{[1
]}

Dubrova, Elena ^{[1
]}

机构：

[1] Royal Inst Technol KTH, Stockholm, Sweden

来源：

2021 IEEE 51ST INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL 2021) | 2021年

关键词：

D O I：

10.1109/ISMVL51352.2021.00035

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

The need of protecting data and bitstreams increases in computation environments such as FPGA as a Service (FaaS). Physically Unclonable Functions (PUFs) have been proposed as a solution to this problem. In this paper, we present an implementation of Arbiter PUF with 4 x 4 switch blocks in Xilinx Series 7 FPGA, perform its statistical analysis, and compare it to other Arbiter PUF variants. We show that the presented implementation utilizes five times less area than 2 x 2 Arbiter PUF-based implementations. It is suitable for many real-world applications, including identification, authentication, key provisioning, and random number generation.

引用

页码：160 / 165

页数：6

共 50 条

[1] Implementation of HEVC Intra 4x4 Prediction on FPGA
Abdellah, Skoudarli
Youcef, Sekkal
Lamine, Djelouat
[J]. 2015 SCIENCE AND INFORMATION CONFERENCE (SAI), 2015, : 1160 - 1164
[2] A Reconfigurable Arbiter PUF with 4 x 4 Switch Blocks
Dubrova, Elena
[J]. 2018 IEEE 48TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL 2018), 2018, : 31 - 37
[3] An Efficient Implementation of Arbiter PUF on FPGA for IoT Application
Mahalat, Mahabub Hasan
Mandal, Suraj
Mondal, Anindan
Sen, Bibhash
[J]. 32ND IEEE INTERNATIONAL SYSTEM ON CHIP CONFERENCE (IEEE SOCC 2019), 2019, : 324 - 329
[4] Implementation of Double Arbiter PUF and Its Performance Evaluation on FPGA
Machida, Takanori
Yamamoto, Dai
Iwamoto, Mitsugu
Sakiyama, Kazuo
[J]. 2015 20TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2015, : 6 - 9
[5] Implementation of Efficient XOR Arbiter PUF on FPGA With Enhanced Uniqueness and Security
Anandakumar, N. Nalla
Hashmi, Mohammad S.
Chaudhary, Muhammad Akmal
[J]. IEEE ACCESS, 2022, 10 : 129832 - 129842
[6] FPGA Implementation of Modeling Attack Resistant Arbiter PUF with Enhanced Reliability
Zalivaka, Siarhei S.
Ivaniuk, Alexander A.
Chang, Chip-Hong
[J]. PROCEEDINGS OF THE EIGHTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED), 2017, : 313 - 318
[7] FpGA implementation of 4x4 MIMO test-bed for spatial multiplexing systems
Cui, MF
Murata, H
Araki, K
[J]. 2004 IEEE 15TH INTERNATIONAL SYMPOSIUM ON PERSONAL, INDOOR AND MOBILE RADIO COMMUNICATIONS, VOLS 1-4, PROCEEDINGS, 2004, : 3045 - 3048
[8] Cross-PUF Attacks: Targeting FPGA Implementation of Arbiter-PUFs
Trevor Kroeger
Wei Cheng
Jean-Luc Danger
Sylvain Guilley
Naghmeh Karimi
[J]. Journal of Electronic Testing, 2022, 38 : 261 - 277
[9] Cross-PUF Attacks: Targeting FPGA Implementation of Arbiter-PUFs
Kroeger, Trevor
Cheng, Wei
Danger, Jean-Luc
Guilley, Sylvain
Karimi, Naghmeh
[J]. JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2022, 38 (03): : 261 - 277
[10] Random Arbiter and Platform level Design for Improving the Performance on 4x4 NoC.
Swamy, Kendaganna S.
Jatti, Anand
Uma, B., V
[J]. 2016 INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONICS, AND OPTIMIZATION TECHNIQUES (ICEEOT), 2016, : 978 - 983

← 1 2 3 4 5 →