65nm full-chip implementation using double dipole lithography

Double Dipole Lithography (DDL(TM)) has been demonstrated to be capable of patterning complex 2D patterns [I]. Due to inherently high aerial imaging contrast, especially for dense features, we have found that it has a very good potential to meet manufacturing requirements for the 65nm node using ArF binary chrome masks. For patterning in the k(1)< 0.35 regime without resorting to hard phase-shift masks (PSMs), DDL is one unique Resolution Enhancement Technique (RET) which can achieve an acceptable process window. To utilize DDL for printing actual IC devices, the original design data must be decomposed into "vertical (V)" and "horizontal (H)" masks for the respective X- and Y-dipole exposures. An improved two-pass, model-based, DDL mask data processing methodology has been established. It is capable of simultaneously converting complex logic and memory mask patterns into DDL compatible mask layout. To maximize the overlapped process window area, we have previously shown that the pattern-shielding algorithm must be intelligently applied together with both Scattering Bars (SBs) and model-based OPC (MOPC)[1]. Due to double exposures, stray light must be well-controlled to ensure uniform printing across the entire chip. One solution to minimize stray light is to apply large patches of solid chrome in open areas to reduce the background transmission during exposure. Unfortunately, this is not feasible for a typical clear-field poly gate masks to be patterned by a positive resist process. In this work, we report a production-worthy DDL mask pattern decomposition scheme for full-chip application. A new generation of DDL technology reticle set has been developed to verify the printing performance. Shielding is a critical part of the DDL. An innovative shielding scheme has been developed to protect the critical features and minimize the impact of stray light during double exposure.