A Design of Multi-Phase Clocks Generator for CDR

As a significant component of phase interpolation based clock and data recovery circuit, the multi-phase clocks generator is used to generating multi-phase clocks for data sampling. Employing the gain-boosting charge pump and the replica bias differential voltage controlled delay line for a 1.6 similar to 2.5Gbps clock and data recovery circuit, a multi-phase clocks generator was designed and implementation in 65nm CMOS standard process with 8 output clocks. Simulation results show that: the operating frequency range of the circuit is 400 similar to 625MHz; the locking time of the circuit is 400ns@625MHz; after the phase is locked, feedback phase error < 30ps, adjacent phase error < 8ps, meeting the requirements of the clock and data recovery circuit.