A Novel interconnection technology using ultra-thin under barrier metal for multiple chip-on-chip stacking structure

被引:1
|
作者
Nakamura, Takuya [1 ]
Shimizu, Kan [1 ]
Maehara, Masataka [1 ]
Hayashi, Toshihiko [1 ]
Akiyama, Kentaro [1 ]
Fujimagari, Junichiro [1 ]
Ohkubo, Tomohiro [2 ]
Fujiwara, Atsushi [2 ]
Iwamoto, Hayato [1 ]
机构
[1] Sony Semicond Solut, Atsugi, Kanagawa, Japan
[2] Sony Semicond Mfg, Kumamoto, Japan
关键词
barrier metal; Chip on Wafer; Co; Ti; Ta;
D O I
10.1109/ECTC.2019.00252
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this report, connectivity and reliability between barrier metal and SnAg solder were evaluated from the viewpoint of intermetallic compound (IMC) growth and reliability behavior. On the basis of previous public research, Co, Ti and Ta were selected as the barrier metal. On the top chip side, 22,000 SnAg solder bumps with 20 um Phi/ 40 um pitch were formed. On the bottom chip side, Al pads with the selected barrier metal were fabricated as an electrode. Connectivity testing of the SnAg bump and barrier metal was carried out by Kelvin resistance, Daisy chain, and cross-sectional SEM. Reliability tests were carried out under high temperature and heat cycling conditions. The results of the connectivity verification revealed similar electric characteristics between SnAg solder and barrier in all barrier metal types. This successful demonstration of sub-micron thickness Co material as a barrier metal of SnAg solder bump connection will enable high reliability one-side soldering with reduced processing costs.
引用
收藏
页码:1641 / 1646
页数:6
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