INVITED Cryo-CMOS Electronic Control for Scalable Quantum Computing

被引:14
|
作者
Sebastiano, Fabio [1 ]
Homulle, Harald [1 ]
Patra, Bishnu [1 ]
Incandela, Rosario [1 ]
van Dijk, Jeroen [1 ]
Song, Lin [1 ,2 ]
Babaie, Masoud [1 ]
Vladimirescu, Andrei [1 ,3 ]
Charbon, Edoardo [1 ,4 ,5 ]
机构
[1] Delft Univ Technol, Beijing, Peoples R China
[2] Tsinghua Univ, Beijing, Peoples R China
[3] Univ Calif Berkeley, Berkeley, CA USA
[4] Intel Corp, Hillsboro, OR 97124 USA
[5] EPFL, Neuchatel, Switzerland
关键词
Cryo-CMOS; cryogenics; quantum computation; qubit; error-correcting loop; device models; MOSFET; TEMPERATURE; ALGORITHMS; COMPACT; QUBIT;
D O I
10.1145/3061639.3072948
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Quantum computers(1) could revolutionize computing in a profound way due to the massive speedup they promise. A quantum computer comprises a cryogenic quantum processor and a classical electronic controller. When scaling up the cryogenic quantum processor to at least a few thousands, and possibly millions, of qubits required for any practical quantum algorithm, cryogenic CMOS (cryo-CMOS) electronics is required to allow feasible and compact interconnections between the controller and the quantum processor. Cryo-CMOS leverages the CMOS fabrication infrastructure while exploiting the continuous improvement of performance and miniaturization guaranteed by Moore's law, in order to enable the fabrication of a cost-effective practical quantum computer. However, designing cryo-CMOS integrated circuits requires a new set of CMOS device models, their embedding in design and verification tools, and the possibility to co-simulate the cryo-CMOS/quantum-processor architecture for full-system optimization. In this paper, we address these challenges by focusing on their impact on the design of complex cryo-CMOS systems.
引用
收藏
页数:6
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