Power-performance trade-offs in nanometer-scale multi-level caches considering total leakage

In this paper, we investigate the impact of T-ox and V-th on power performance trade-offs for on-chip caches. We start by examining the optimization of the various components of a single level cache and then extend this to two level cache systems. In addition to leakage, our studies also account for the dynamic power expended as a result of cache misses. Our results show that one can often reduce overall power by increasing the size of the L2 cache if we only allow one pair Of V-th/T-ox., in L2. However, if we allow the memory cells and the peripherals to have their own V-th's and T-ox's, we show that a two-level cache system with smaller L2's will yield less total leakage. We further show that two V-th's and two T-ox's are sufficient to get close to an optimal solution, and that V,h is generally a better design knob than T-ox for leakage optimization, thus it is better to restrict the number of T-ox's rather than V-th's if cost is a concern.