Study of FPGA implementations of scheduling algorithms for high-performance switches

被引：0
|
作者：
Lago, Elena [1 ]
Soto, Enrique [1 ]
Rodriguez-Andina, Juan J. [1 ]
机构：
[1] Univ Vigo, Dept Elect Technol, Vigo, Spain
来源：
2007 IEEE INTERNATIONAL SYMPOSIUM ON INDUSTRIAL ELECTRONICS, PROCEEDINGS, VOLS 1-8 | 2007年
关键词：
D O I：
10.1109/ISIE.2007.4374978
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
One of the most important issues in current high-performance packet switches is the availability of efficient algorithms to maximize instantaneous throughput. (D)PHM and iSLIP are well-known algorithms for virtual output-queued switches. In this paper, a comparative study of the implementation of both types of schedulers in different families of FPGAs is presented. Experimental results show that, in addition to the well known advantages of using field-programmable logic, the proposed implementations provide a performance-complexity trade-off which makes them a suitable practical alternative for high-performance scheduling tasks.
引用
收藏
页码：2374 / 2379
页数：6
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