共 4 条
- [1] Effective intrinsic gettering for 200mm and 300mm P/P- wafers in a low thermal budget 0.13μm advanced CMOS logic process SEMICONDUCTOR SILICON 2002, VOLS 1 AND 2, 2002, 2002 (02): : 647 - 657
- [2] 0.12 μm P-MOSFETs with high-K and metal gate fabricated in a Si process line on 200mm GeOI wafers ESSDERC 2007: PROCEEDINGS OF THE 37TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2007, : 458 - 461
- [3] Experimental Realization of Complementary p- and n- Tunnel FinFETs with Subthreshold Slopes of less than 60 mV/decade and Very Low (pA/μm) Off-Current on a Si CMOS Platform 2014 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2014,
- [4] A X-band frequency synthesizer with 2-bit control mode is implemented in standard 0.18-μm 1P6M CMOS process. A cascoded topology of voltage control oscillator (VCO) and first stage current mode logic (CML) divider is adopted for current reuse, low power, and robust tracking between VCO and the frequency divider. The measured in-band phase noise of the synthesizer is-75.06 dBc/Hz at a frequency offset of 100 kHz and out-of-band phase noise is-119.8 dBc/Hz at a frequency offset of 10 MHz. The total power consumption is 36.75 mW. The chip size is 0.745 x 0.76mm2. 2012 ASIA-PACIFIC MICROWAVE CONFERENCE (APMC 2012), 2012, : 1226 - 1228