Twisted differential on-chip interconnect architecture for inductive/capacitive crosstalk noise cancellation

被引：1
|
作者：
Hatirnaz, I [1 ]
Leblebici, Y [1 ]
机构：
[1] Swiss Fed Inst Technol, EPFL, LSM, CH-1015 Lausanne, Switzerland
来源：
INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP, PROCEEDINGS | 2003年
关键词：
D O I：
10.1109/ISSOC.2003.1267725
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A simple generic interconnect architecture is presented to allow effective cancellation of inductive and capacitive noise in high-speed on-chip interconnect lines. The approach is based on the principle of constructing periodically twisted differential line pairs for parallel interconnect segments in order to eliminate the mutual coupling influences. Detailed 3-D simulations show that a crosstalk noise reduction of up to 60 dB is achievable with this approach.
引用
收藏
页码：93 / 96
页数：4
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