The Design of High Speed Data Acquisition System Based on JESD204B

被引：0
|
作者：
Wang, Yu [1 ]
Shi, Qingzhan [1 ]
Feng, Qi [1 ]
机构：
[1] Natl Univ Def Technol, Coll Elect Sci & Engn, Changsha 410073, Hunan, Peoples R China
来源：
PROCEEDINGS OF THE 2ND INTERNATIONAL CONFERENCE ON COMPUTER ENGINEERING, INFORMATION SCIENCE & APPLICATION TECHNOLOGY (ICCIA 2017) | 2017年 / 74卷
关键词：
Data acquisition system; JESD204B interface; High-speed ADC;
D O I：
暂无
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
Recently, various acquisition systems require data converters to provide higher resolution and sampling rates. The physical layout of parallel interfaces and the bit rate limitations of serial LVDS methods pose technical hurdles for designers. The design is based on the classical architecture of FPGA+ DSP+ ADC of data acquisition system. The High speed ADC is based on JESD204B interface with four slices and two channels, it can meet the requirements of high-speed acquisition, and high-speed sampling of eight channels. It provides a good method for the design and application of various high-speed acquisition systems, and it effectively solves all kinds of problems in parallel transmission of traditional data acquisition, and brings great engineering application value.
引用
收藏
页码：797 / 801
页数：5
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