The Improvement of High-k/Metal Gate pMOSFET Performance and Reliability Using Optimized Si Cap/SiGe Channel Structure

被引：19

作者：

Yeh, Wen-Kuan ^{[1
]}

Chen, Yu-Ting ^{[2
]}

Huang, Fon-Shan ^{[2
]}

Hsu, Chia-Wei ^{[3
]}

Chen, Chun-Yu ^{[3
]}

Fang, Yean-Kuen ^{[3
]}

Gan, Kwang-Jow ^{[4
]}

Chen, Po-Ying ^{[5
]}

机构：

[1] Natl Univ Kaohsiung, Dept Elect Engn, Kaohsiung 811, Taiwan

[2] Natl Tsing Hua Univ, Inst Elect Engn, Hsinchu 300, Taiwan

[3] Natl Cheng Kung Univ, Inst Elect Engn, Tainan 70101, Taiwan

[4] Natl Chiayi Univ, Dept Elect Engn, Chiayi 60004, Taiwan

[5] I Shou Univ, Dept Informat Engn, Kaohsiung 840, Taiwan

来源：

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY | 2011年 / 11卷 / 01期

关键词：

High-k/ Metal Gate; pMOSFET; SiGe substrate; TRANSPORT; STRAIN;

D O I：

10.1109/TDMR.2010.2065806

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The impact of the Si cap/SiGe layer on the Hf-based high-k/metal gate SiGe channel pMOSFET performance and reliability has been investigated. We proposed an optimized strain SiGe channel with a Si cap layer to overcome the Ge diffusion and confine the channel carriers in the strained SiGe layer without the formation of a significant parasitic channel at the interface. With this optimized Si/SiGe stack channel, a high-performance Hf-based high-k/metal gate SiGe pMOSFET can be obtained with an appropriate V-TH (similar to 0.3 V), low C-V hysteresis (< 5 mV), and better I-ON - I-OFF, V-TH rolloff, and V-TH stability. By the way, the related interface trap density in the high-k gate stack layer can also be reduced, thus improving the device's NBTI and HCI stressing-induced reliability.

引用

页码：7 / 12

页数：6

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