Off-line testing of asynchronous circuits

被引：3

作者：

Koppad, D ^{[1
]}

Bystrov, A ^{[1
]}

Yakovlev, A ^{[1
]}

机构：

[1] Newcastle Univ, Newcastle Upon Tyne NE1 7RU, Tyne & Wear, England

来源：

18TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: POWER AWARE DESIGN OF VLSI SYSTEMS | 2005年

关键词：

D O I：

10.1109/ICVD.2005.126

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A new technique to test asynchronous circuits obtained by direct mapping technique from 1-safe Petri nets is proposed. Low-level physical faults in the cells implementing Petri net places are analysed and mapped into high-level specification, a Petri net. A "pseudo clock" is used to handle hazards and activate faults which exhibit themselves only under particular arrangements. Asynchronous citcuit obtained by Direct mapping technique can be made 100% testable for stuck-at-faults by implementing testability features. An algorithm to insert testability features and generate test sequences is presented using a benchmark.

引用

页码：730 / 735

页数：6

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