Novel and robust constant-gm technique for rail-to-rail CMOS amplifier input stages

We present a new circuit technique for rail-to-rail constant-transconductance (g(m)) CMOS amplifier input stages, achieving constant transconductance and slew rate over the full input common-mode voltage range without degrading high-frequency performance. In addition, the technique does not rely on the quadratic characteristic of the input MOS transistors, and is robust to transconductance parameter mismatch between N and P input transistors. A CMOS amplifier input stage is designed in a standard 0.35-mu m CMOS process. With a 3-V supply, the g(m) variation is kept within +/- 1% under nominal conditions and +/- 3% when there is 40% mismatch of input transistor transconductance parameters. In addition, 114-MHz gain-bandwidth product is achieved with a 2 pF capacitive load. The proposed input stage can be applied in communications and VLSI cell libraries.