High Performance Emulation of Quantum Circuits

被引:0
|
作者
Haner, Thomas [1 ]
Steiger, Damian S. [1 ]
Smelyanskiy, Mikhail [2 ]
Troyer, Matthias [1 ,3 ]
机构
[1] Swiss Fed Inst Technol, Inst Theoret Phys, CH-8093 Zurich, Switzerland
[2] Intel Corp, Parallel Comp Lab, Hillsboro, OR 97124 USA
[3] Microsoft Res, Quantum Architectures & Computat Grp, Redmond, WA 98052 USA
基金
瑞士国家科学基金会;
关键词
D O I
暂无
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
As quantum computers of non-trivial size become available in the near future, it is imperative to develop tools to emulate small quantum computers. This allows for validation and debugging of algorithms as well as exploring hardware-software co-design to guide the development of quantum hardware and architectures. The simulation of quantum computers entails multiplications of sparse matrices with very large dense vectors of dimension 2(n), where n denotes the number of qubits, making this a memory-bound and network bandwidth-limited application. We introduce the concept of a quantum computer emulator as a component of a software framework for quantum computing, enabling a significant performance advantage over simulators by emulating quantum algorithms at a high level rather than simulating individual gate operations. We describe various optimization approaches and present benchmarking results, establishing the superiority of quantum computer emulators in terms of performance.
引用
收藏
页码:866 / 874
页数:9
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