Advanced materials for low power electronics

This paper will review recent advances in the development of key material structures essential for the cost effective manufacture of promising low power technology candidates such as scaled CMOS [bulk/silicon-on-insulator (SOI)], BiCMOS and HBTs. The introduction of a new breed of 200/300 mm substrates, such as ultra-thin SOI and low cost intrinsically gettered bulk Si (e.g., hydrogen annealed, buried layers) for the front-end process and low K dielectric materials (polymers, aerogels, etc.) and Cu metallization for the interconnects, will play major roles in meeting the performance (maximum speed at minimum power at V-dd = 1 V), manufacturability and cost requirements driving the low power paradigm. The material requirements and timing for their introduction into manufacturing need to be in concert with their anticipated insertion into the 0.25/0.18 mu m technology nodes for both memory and logic (mu P) applications. A critical review of the major manufacturing challenges facing these material systems will be discussed.