A shared-well dual-supply-voltage 64-bit ALU

被引:0
|
作者
Shimazaki, Y [1 ]
Zlatanovici, R [1 ]
Nikoli, B [1 ]
机构
[1] Hitachi, Tokyo, Japan
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
引用
收藏
页码:104 / +
页数:3
相关论文
共 24 条
  • [1] A shared-well dual-supply-voltage 64-bit ALU
    Shimazaki, Y
    Zlatanovici, R
    Nikolic, B
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (03) : 494 - 500
  • [2] Suppression of On-Chip Power Supply Noise Generated by a 64-Bit Static Logic ALU Block
    Charania, Tasreen
    Chuang, Pierce
    Opal, Ajoy
    Sachdev, Manoj
    2012 IEEE/IFIP 20TH INTERNATIONAL CONFERENCE ON VLSI AND SYSTEM-ON-CHIP (VLSI-SOC), 2012, : 201 - 206
  • [3] A 64-bit, shared disk file system for Linux
    Preslan, KW
    Barry, AP
    Brassow, JE
    Erickson, GM
    Nygaard, E
    Sabol, CJ
    Soltis, SR
    Teigland, DC
    O'Keefe, MT
    INFORMATION-BASED ACCESS TO STORAGE: THE FOUNDATION OF INFORMATION SYSTEMS, PROCEEDINGS, 1999, : 22 - 41
  • [4] Lightweight shared objects in a 64-bit operating system
    Chase, Jeffrey S.
    Levy, Henry M.
    Lazowska, Edward D.
    Baker-Harvey, Miche
    SIGPLAN Notices (ACM Special Interest Group on Programming Languages), 1992, 27 (10):
  • [5] LIGHTWEIGHT SHARED OBJECTS IN A 64-BIT OPERATING SYSTEM
    CHASE, JS
    LEVY, HM
    LAZOWSKA, ED
    BAKERHARVEY, M
    SIGPLAN NOTICES, 1992, 27 (10): : 397 - 413
  • [6] A 4-GHz 300-mW 64-bit integer execution ALU with dual supply voltages in 90-nm CMOS
    Mathew, SK
    Anders, MA
    Bloechel, B
    Nguyen, T
    Krishnamurthy, RK
    Borkar, S
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2005, 40 (01) : 44 - 51
  • [7] Design and Implementation of Low Power Clock Gated 64-Bit ALU on Ultra Scale FPGA
    Gupta, Ashutosh
    Murgai, Shruti
    Gulati, Anmol
    Kumar, Pradeep
    PROCEEDINGS OF THE 2ND INTERNATIONAL CONFERENCE ON COMMUNICATION SYSTEMS (ICCS-2015), 2016, 1715
  • [8] A transparent voltage conversion method and its application to a dual-supply-voltage register file
    Tzartzanis, N
    Walker, WW
    21ST INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, PROCEEDINGS, 2003, : 107 - 110
  • [9] 64-bit hybrid dual-threshold voltage power-aware conditional carry adder design
    Cheng, KH
    Cheng, SW
    Huang, CW
    4TH IEEE INTERNATIONAL WORKSHOP ON SYSTEM-ON-CHIP FOR REAL-TIME APPLICATIONS, PROCEEDINGS, 2004, : 65 - 68
  • [10] Minimizing energy consumption based on dual-supply-voltage assignment and interconnection simplification
    Hariyama, Masanori
    Yamadera, Shigeo
    Kameyama, Michitaka
    IEICE TRANSACTIONS ON ELECTRONICS, 2006, E89C (11) : 1551 - 1558