Acceleration of feature extraction for FPGA based speech recognition

被引:2
|
作者
Arminas, Vytautas [1 ]
Tamulevicius, Gintautas [2 ]
Navakauskas, Dalius [1 ]
Ivanovas, Edgaras [1 ]
机构
[1] Vilnius Gediminas Tech Univ, Dept Elect Syst, Naugarduko Str 41, Vilnius, Lithuania
[2] Inst Math & Informat, Recognit Proc Dept, Vilnius, Lithuania
关键词
Field programmable gate array; feature extraction; cepstral analysis; speech recognition;
D O I
10.1117/12.872081
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The paper describes a field programmable gate array implementation of the main part of speech recognition system - feature extraction. In order to accelerate recognition the whole cepstral analysis scheme is implemented in hardware by the use of intellectual property cores. Two field programmable gate array devices are used for evaluation. Comparative experimental results of four different implementations are presented. They grounds achieved 29 times faster speech analysis in comparison with software based analysis subsystem.
引用
收藏
页数:6
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