A Theoretical Study of Error Mechanisms in Switched-Current Circuits

This paper describes a theoretical study of the main errors in switched-current (SI) cells, such as conductance ratio error, settling time error and charge injection error, and their influence on the output/input transfert characteristic. First, our interest is focused on the study each error mechanism and its effect on the SI memory cell. After that, we studied the influence of their cumulative effect Finally, we detailed the effect of cumulative error on the integrator level. The most significant non-idealities of SI cell are identified and their cumulative effect on SI cell and SI integrator transfert characteristic are analytically demonstrated.