Obtaining hardware performance metrics for the BlueGene/L supercomputer

Hardware performance monitoring is the basis of modem performance analysis tools for application optimization. We are interested in providing such performance analysis tools for the new BlueGene/L supercomputer as early as possible, so that applications can be tuned for that machine. We are faced with two challenges in achieving that goal. First, the machine is still going through its final design and assembly stages and, therefore, it is not yet available to system and application programmers. Second, and most important, key hardware performance metrics, such as instruction counters and Level 1 cache behavior counters, are missing from the BlueGene/L architecture. Our solution to those problems has been to implement a set of nonarchitected performance counters in an instruction-set simulator of BlueGene/L, and to provide a mechanism for executing code to retrieve the value of those counters. Using that mechanism, we have ported a version of the libHPM performance analysis library. We validate our implementation by comparing our results for BlueGene/L to analytical models and to results from a real machine.