Design Techniques for External Capacitor-less LDOs with High PSR over Wide Frequency Range

被引：0

作者：

Park, Chang-Joon ^{[1
]}

Silva-Martinez, Jose ^{[1
]}

Onabajo, Marvin ^{[2
]}

机构：

[1] Texas A&M Univ, Dept Elect & Comp Engn, AMSC, College Stn, TX 77843 USA

[2] Northeastern Univ, Dept Elect & Comp Engn, Boston, MA 02115 USA

来源：

2014 IEEE 57TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS) | 2014年

关键词：

Low drop-out (LDO); external capacitor-less LDO; power supply rejection (PSR); power management; system-on-chip (SoC); DROP-OUT REGULATOR;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

The paths for power supply noise leakage in low drop-out (LDO) voltage regulators are analyzed, and techniques are discussed to minimize their effects on the output voltage. An internally compensated high power supply rejection (PSR) LDO voltage regulator with adaptive supply noise compensation scheme is presented. Its regulated output voltage is 1.6 V to provide 0-50 mA of current with a power supply of 1.8 V. The measured PSR is better than -50 dB up to 4 MHz. The fabricated LDO occupies 0.25 mm(2) in a 0.18 mu m CMOS technology. It consumes 80 mu A of ground current. The load regulation for a 50 mA step with 100 ns rise/fall times is 200 mV.

引用

页码：342 / 345

页数：4

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