Nanoimprint System Development and Status for High Volume Semiconductor Manufacturing

Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash Imprint Lithography (J-FIL) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. Criteria specific to any lithographic process for the semiconductor industry include overlay, throughput and defectivity. The purpose of this paper is to describe the technology advancements made and introduce the new imprint systems that will be applied for the fabrication of advanced devices such as NAND Flash memory and DRAM. Overlay of better than 5nm (mean + 3sigma) has been demonstrated, and throughputs of 10 wafers per imprint station are now routinely achieved. Defectivity has been reduced by more than two orders of magnitude and particle adders within the tool have come down by approximately four orders of magnitude. A pilot line tool, the FPA-1100 NZ2, was used to generate most of the results in this work and conceptual plans are in place to address the requirements necessary for high volume manufacturing with an attractive cost of ownership relative to other HVM solutions for the semiconductor industry.