Run-Time Reconfiguration of Processing Elements through Soft-Core Processor

被引:0
|
作者
Nithya, R. [1 ]
Chandran, K. R. Sarath [2 ]
Chandramani, V. Premanand [1 ]
机构
[1] SSN Coll Engn, Dept Elect & Commun Engn, Madras, Tamil Nadu, India
[2] SSN Coll Engn, Dept Comp Sci Engn, Madras, Tamil Nadu, India
关键词
Nios II; Processing elements; Reconfigurable architectures; Run Time reconfiguration; Soft core processors; System-on-Chip;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper proposes a system-on-chip design to perform run-time reconfiguration using soft-core processor. The reconfigurable module consists of a set of Processing Elements (PEs) that are fully connected to each other through a crossbar network. Run-time reconfiguration is achieved by dynamically selecting the desired number of PEs based on the input data set through soft-core processor. This dynamic selection of PEs leads to optimum resource utilization and lesser power consumption for computationally intensive applications such as media processing. Optimization was achieved through minimizing number of logic elements, total fan-out, and total power dissipation for systems with varying number of processing elements.
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页数:5
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