Analysis and Modeling of Router Based on M/D/1/B Queuing Model for Networks-on-Chip

To establish a kind of highly-efficient analytical performance model for the router-design of networks-on-chip at the early stage is crucial. Firstly, according to the generalized router architecture, a variety of waiting phenomena of the packets at the input buffers during the transfer process are analyzed in this paper, and then an analytical router performance model which is based on M/D/1/B queuing system is proposed. Secondly, we present a computing method for flow control feedback probability from its immediate neighbor based on Markov chain. Finally, the relationship between the flow control feedback probability and the size of input buffers are analyzed, as well as the number of pipeline stages of router. The approached model can be used to guide the design of router architecture for networks-on-chip.