Design of superconductor frame compression circuits

We proposed previously a novel interface circuit which was used between semiconductor data-input circuits and superconductor highspeed routers. The frame length of data packets is compressed in the interface circuit. Our proposed interface circuit has rather narrow timing margin. The problem was that our control circuit of the interface circuit could allow only very small timing delay. In this paper we propose a modified control circuit. We have improved the timing margin of the control circuit using RS-flip flop (RS-FF), where two shift registers and one control circuit are driven by clock pulses provided from a master clock-pulse generator. In this circuit, we have assumed fixed frame length packets. Our final target of master clock frequency is 100 GHz which will be realized with the device-parameter set of future advanced process. As the first step of realizing this target value, we aimed at 40 GHz clock operation with the conventional device-parameter set of NECs standard I process. The behavior of the whole frame compression circuit was simulated by a computer, and it was confirmed that it operated properly up to the master clock frequency of 23 GHz. (C) 2007 Elsevier B.V. All rights reserved.