High-κ gate dielectrics with ultra-low leakage current for sub-45 nm CMOS

被引：4
|
作者：
Venkateshan, A. [1 ]
Singh, R.
Poole, K. F.
Harriss, J.
Senter, H.
Teague, R.
Narayan, J.
机构：
[1] Clemson Univ, Dept Elect & Comp Engn, Clemson, SC 29634 USA
[2] Clemson Univ, Dept Math, Clemson, SC 29634 USA
[3] Clemson Univ, Comp & Network Serv, Clemson, SC 29634 USA
[4] N Carolina State Univ, Dept Mat Sci & Engn, Raleigh, NC 27695 USA
来源：
ELECTRONICS LETTERS | 2007年 / 43卷 / 21期
关键词：
D O I：
10.1049/el:20072178
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The results of a new method of high-kappa dielectric formation are reported. For effective oxide thickness of 0.39 nm, the leakage current density of metal-high-kappa-silicon structure is about 1 x 10(-12) A/cm(2) for gate voltage from +3 to -3 V The descriptive statistics and process variation data presented demonstrate that the process is robust and manufacturing tools can be developed without any fundamental barrier.
引用
收藏
页码：1130 / 1132
页数：3
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