Implementation of a 17 bits Pulse Width Modulation Circuit using FPGA

被引：0
|
作者：
Salomon, Lucas [1 ]
Moreno, Robson [1 ]
Pimenta, Tales [1 ]
机构：
[1] Univ Fed Itajuba, Itajuba, Brazil
来源：
2015 27TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS (ICM) | 2015年
关键词：
Digital pulse width modulator (DPWM); carry chain; field-programmable gate arrays (FPGA); high resolution; RESOLUTION;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents the implementation of a 17 bits digital pulse width modulator (DPWM). Smaller pulses were obtained using internal carry chains that are available in many FPGAs. Our proposed architecture minimizes the critical paths that influence the linearity and induces the creation of carry chains without the use of adders. The frequency of the DPWM is 90.5kHz with a resolution of approximately 80ps, and the clock frequency is 46.34MHz.
引用
收藏
页码：206 / 209
页数：4
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