IN PURSUIT OF INSTANT GRATIFICATION FOR FPGA DESIGN

This paper describes an alternative FPGA design compilation flow to reduce the back-end time required to implement a Xilinx FPGA design. Using a library of pre-compiled modules and associated meta-data, bitstream-level assembly of desired designs can occur in a fraction of the time of traditional back-end tools. Modules are bound, placed, and routed using custom bitstream assembly with the primary objective of rapid compilation while preserving performance. Since vendor tools are not needed for assembly, compilation can be performed in embedded and/or untethered environments. As a result, large device compilations can be assembled in seconds. This turbo flow (TFlow) enables software-like turn-around time for faster prototyping and increased productivity.