3D Integration of CMOS-compatible Surface Electrode Ion Trap and Silicon Photonics for Scalable Quantum Computing

In this work, we report ion trap fabrication using prevailing foundry copper back-end-of-line process on a 300mm Si platform. Surface electrodes comprising of similar to 3.7 mu m thick Cu and similar to 0.2 gm thick of Au surface finish are electroplated above a similar to 3 mu m thick of SiO2 layer on a high-resistivity Si substrate. The innovative process, which is fully compatible with CMOS back-end, enables a fine gap trench structure between the electrodes, such that the exposed dielectric area to the trapped ions is reduced. By optimizing the electroplating process, a relatively flat Cu surface is created with a thin Au layer deposited as an effective protective layer to prevent surface oxidation. The fabricated trap is wire-bonded in a CPGA package for DC and RF testing. Small size Si traps show a good RF dissipation property which is a prerequisite for ion trapping. The further integration of TSV and Si photonics shows a promising prospect in terms of electrical and optical performance enhancement of ion trap.