Reliability improvement of Cu interconnects by additional anneal between CuCMP and barrier CMP

被引：6

作者：

Harada, T ^{[1
]}

Kobayashi, K ^{[1
]}

Takahashi, M ^{[1
]}

Nii, K ^{[1
]}

Ikeda, A ^{[1
]}

Ueda, T ^{[1
]}

Yabu, T ^{[1
]}

机构：

[1] Matsushita Elect Ind Co Ltd, ULSI Proc Technol Dev Ctr, Minami Ku, Kyoto 6018413, Japan

来源：

PROCEEDINGS OF THE IEEE 2003 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE | 2003年

关键词：

D O I：

10.1109/IITC.2003.1219722

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The new technology which improves the reliability of Cu interconnects has been developed. In this technology, an anneal is carried out after a Cu CMP, followed by a barrier CMP and a p-SiN deposition. As a result, electromigration (EM) lifetime and stress-induced voiding (SIV) resistance have been improved drastically without the degradation of device performance and yield. Structural analyses suggest that the reliability improvement is realized by the reduction of tensile stress due to the stabilization of the Cu films and the minimization of the contact area of p-SiN/Cu interface due to the surface smoothing.

引用

页码：92 / 94

页数：3

共 49 条

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