A low noise high linearity CMOS upconversion mixer

被引：0
|
作者：
Jin, Liming [1 ]
Tang, Zhangwen [1 ]
Min, Hao [1 ]
机构：
[1] Fudan Univ, State Key Lab ASIC & Syst, Shanghai 201203, Peoples R China
来源：
ASICON 2007: 2007 7TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS | 2007年
关键词：
D O I：
10.1109/ICASIC.2007.4415659
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, a low noise high linearity mixer is presented, exploiting a switched transconductor topology. Its noise figure (NF) and linearity are analyzed particularly. The mixer chip is implemented in 0.18-mu m RF CMOS process. The measurement result shows that the conversion gain of the mixer is about 8dB, the SSB NF is about 11dB, and the input-referred third-order intercept point (IIP3) is about 10.5dBm. The chip consumes 10mA at 1.8V power supply and the size of the whole chip is 0.63mmx0.78mm.
引用
收藏
页码：431 / 434
页数：4
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