Design and Comparison of High Bandwidth Limiting Amplifier Topologies

This paper describes and compares many of inductorless limiting amplifier topologies that have been introduced in the technical literature so far. We start with resistor loaded NMOS differential amplifier as a reference to our work. Then we investigate bandwidth enhancement techniques such as negative Miller capacitance, active shunt peaking, active feedback and negative impedance conversion. We also propose an improvement for active shunt peaking topology to reduce ISI jitter especially for large input signals. Maximum input loading of amplifiers is specified as 250fF and output loading can be as high as 50fF. Therefore, inverse scaling technique is applied in all amplifiers to further increase the bandwidth. All topologies are designed in 0.18 mu m CMOS technology and were simulated in Cadence Design Environment. They are designed for a voltage gain of 32dB and 1.2Vpp output voltage swing. Each of them consumes 54mW to make a fair comparison.